1. Field of the Invention
This invention relates to methods and systems for use in defect inspection of microfabricated structures such as integrated circuit die on semiconductor wafers, masks or reticles for microfabrication, flat panel displays, micro-electromechanical (MEMs) devices and the like during and after manufacture. In particular, the invention provides methods and systems for more effectively and efficiently inspecting microfabricated structures that are repetitive in nature such as memory cells including SRAM, DRAM, FRAM, Flash memory, repetitive programmable logic ICs such as PLAs, PLDs, MEMs displays repetitive pixel structures and flat panel displays with repetitive pixel structures and the like.
2. Prior Art
Over the past decade, defect inspection to detect microscopic manufacturing defects has become a standard part of microfabrication manufacturing flows, especially for semiconductor wafers.
Various types of inspection technology are in use including bright-field optical inspection with, for example, a KLA-Tencor 2138 and 2139 made by KLA-Tencor of San Jose Calif., dark-field inspection with for example a KLA-Tencor AIT2 also made by KLA-Tencor. More recently e-beam inspection, with for example Odyssey 300 by Schlumberger Technologies Inc. of San Jose, Calif. or a KLA-Tencor eS20XP made by KLA-Tencor, is emerging as an important inspection technology especially for very advanced sub 0.25 um design rule manufacturing processes.
Each type of inspection technology is usually applied at steps in the semiconductor manufacturing flow where it is best suited to the types of defects most likely to be found. The economic benefits of inspection have been substantial and inspection is generally accepted as having made a significant contribution to the substantial increase in semiconductor wafer manufacturing yields seen in the 1990s.
Inspection systems are employed in a number of different applications including:                process monitoring to flag when a particular process step in the manufacturing flow has an increased defect density above the level normally expected at that step;        problem solving by inspecting so-called short-loop wafers that have only been processed with a subset of the manufacturing process steps in order to facilitate troubleshooting and diagnosis or optimization of a particular subset of process steps and        during process development—to optimize a new manufacturing process to reduce or eliminate process-specific or systematic defect mechanisms.        
Wafer inspection systems for patterned wafer inspection usually work as follows. A high powered microscope, traditionally an optical microscope, but more recently a SEM (Scanning Electron Microscope) or electron microscope, is set up under computer control to acquire sequentially images or contrast data of the area of the microfabricated structures or wafers to be inspected. To minimize the overhead of wafer stage movement and settling time during the inspection process, continuous scanning motion mechanical stages are used such as that described in U.S. Pat. No. 6,252,705 to Lo et al. These stages are specifically designed to have very smooth motion in at least one scanning axis to facilitate accurate image data acquisition without stage noise. In the case of an optically based inspection system, a TDI-CCD (Time Delay Integration-Charged Couple Device) image sensor is often used and synchronized with the scanning motion of the continuous scanning stage to acquire images rapidly. In the case of an e-beam inspection system, the scanning motion of the beam is synchronized with the scanning stage motion to acquire images rapidly.
The image or contrast data that is acquired in this manner is then compared to reference data. Defects are found or detected where there are differences between the reference and the acquired images. The reference images may be derived from CAD data as is often the case with mask or reticle inspection or may simply be images of neighboring cells or die on the wafer or similar wafer being inspected. The sensitivity of the defect inspection process to small defects can be controlled by adjusting the image acquisition parameters such as pixel size, contrast, brightness, charging and bias conditions etc., and image processing parameters that are used to compare the acquired inspection images and reference images.
When repetitive structures such as memory cells and the like are inspected, it is common practice to compare a memory cell with its neighboring cells or with a golden memory cell (often referred to as array or array mode inspection) as is described, for example in U.S. patent to Tsai et al. U.S. Pat. No. 4,845,558 “Method and Apparatus For Detecting Defect in Repeated Micro-miniature Patterns”. Array mode inspection has advantages over random mode inspection due to the inherent similarity of neighboring cells in an array (random mode inspection is used for inspecting random logic or non-repetitive regions with reference data, for example, from other dice on the wafer). Neighboring cells often provide an excellent reference in array inspection as the cell reference itself will be very similar to the inspected cell and the cell image will include very similar imaging aberrations, artifacts or errors from what ever microscope is being used for inspection. Note that the image aberrations, artifacts and errors tend the cancel during the comparison process to find defects and are thus effectively eliminated. This results in increased sensitivity to defects in array mode inspection (versus random mode inspection). This advantage can alternatively be used to provide correspondingly higher throughput in array mode inspection as a result of being able to inspect with a larger pixel size at the same level of defect size sensitivity.
With Tsai et al's approach “the image is magnified to a scale so that features of the patterns repeated in the image occupy corresponding pixels or groups of pixels repeated in the array. Data is resolved from selected pixels and directly compared either to data obtained from corresponding pixels or from a database, whereby defective features are identified through well-known data comparison techniques.”
However, this approach to inspecting array or repetitive areas and the approach used on commercial defect inspection systems available today have some important disadvantages, specifically:                the edges of the repetitive array area must be defined manually before inspection. This can be and often is an extremely time consuming and tedious process especially on advanced memory ICs where the actual area of truly 100% continuous accurately repetitive areas is rather limited. For example, real-world memory arrays are often comprised of large numbers of relatively small repetitive areas surrounded by non-repetitive and partially repetitive areas containing power supply distribution, decode logic and sense-amplifiers that often cannot be satisfactorily inspected with array inspection techniques. Each truly repetitive array segment must be identified manually before inspection.        adjoining non-repetitive segments must be inspected with a separate inspection algorithm for random areas requiring a time consuming second pass of the inspection tool effectively cutting actual tool throughput by 50% or more.        array edges are often not inspected as the accuracy of definition of the array boundaries is limited by inspection system overall position accuracy (stage errors, encoder errors, alignment errors and other error sources combined) and must include a buffer or exclusion zone at the edge of the array to ensure that false defect counts or false alarms are not generated when inadvertently inspecting non-repetitive regions surrounding the repetitive regions when for example accuracy limits are reached.        